1. Field of the Invention
The present invention relates to field effect transistors (FETs) in integrated circuit devices such as semiconductor chips and, in particular, to the formation of halo regions in FETs to moderate and control short-channel effects.
2. Description of Related Art
Halo regions, e.g., diffused boron, have been implanted adjacent the source and drain regions of FET integrated circuit devices in semiconductor chips, as disclosed in U.S. Pat. No. 5,744,841. Halos have been used in transistor device design to moderate short channel effects of advanced FETs devices with very short channel length. It has been found that halos also produce an unwanted phenomena called roll-up which degrades device performance. Roll-up refers to threshold voltages that initially increase as channel length decreases from what is considered a very long value for a given technology. Ultimately, as the channel length approaches the technology minimum, the short channel effect dominates and threshold voltage values rapidly decrease with decreasing channel length.
A method of forming diffusions for high performance FETs using a localized high energy laser has been previously proposed. This process is known as the Projection Gas Immersion Laser Dopant Process (PGILD). PGILD uses a masked laser to selectively dope regions on the wafer n-type or p-type by selectively projecting the laser on a semiconductor wafer through a mask, thus eliminating the need for photoresist and all of the associated tooling and processes for depositing, developing and stripping photoresist.
The PGILD process for forming diffusions can be summarized as follows. The silicon wafer surface to be doped is amorphized, i.e., converted to an amorphous state, usually by ion implantation. The wafer is exposed with a masked laser consistent with block level lithography specifications, in an ambient atmosphere containing an n-type or p-type dopant gases. This first laser exposure causes the dopant to precipitate onto the wafer surface, but without annealing the silicon so that it remains in its amorphous state. A second laser operating at a wavelength of, for example, 308 nm, is then used to anneal the silicon by locally melting the amorphous silicon. The amorphous silicon has a much lower melting point than single crystal silicon, and the energy dose is controlled so that the melting propagates to the amorphous-single crystal silicon (SCS) interface and stops, without melting the single crystal silicon. The surface dopants readily diffuse through the melt, but because the time at temperature is extremely short, do not diffuse into the single crystal silicon. As a result, highly doped, very shallow junctions are created.
Since halos created by the PGILD process are subject to the aforedescribed roll-up phenomena as channel length decreases, it would be advantageous to develop a process which overcomes the problem of the short channel effects and threshold voltage decrease with decreasing channel length.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a process which overcomes the problem of the aforedescribed roll-up phenomena, including short channel effect and threshold voltage decrease with decreasing channel length.
It is another object of the present invention to provide an improved process for manufacturing FETs in integrated circuit devices using the PGILD process.
A further object of the invention is to provide a process for creating a more ideal halo in FETs.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method for fabricating FETs with abrupt halos. Initially, there is provided an initial FET structure having a substrate, a dielectric layer over a portion of the substrate, a gate over the dielectric layer, sidewall insulators on either side of and adjacent the dielectric layer and gate, and halo regions comprising an n- or p-type dopant extending to a desired depth in the substrate adjacent each of the sidewall insulators and beneath a portion of the dielectric layer. The method is practiced by creating first amorphous regions within a portion of each of the halo regions to a depth less than the halo regions and implanting in and diffusing throughout only the first amorphous regions a dopant opposite the n- or p-type dopant used in the halo region to create extension source and drain regions. The method then involves forming dielectric spacers adjacent the sidewall insulators and creating second amorphous regions adjacent each of the dielectric spacers to a depth greater than the halo regions. Thereafter, there is implanted in and diffused throughout only the second amorphous regions a dopant opposite the n- or p-type dopant used in the halo region to create source and drain regions.
The halo regions in the initial FET structure may be formed by creating initial amorphous regions in the substrate adjacent the sidewall insulators using ion implantation and implanting an n- or p-type dopant within the initial amorphous regions and diffusing the dopant throughout substantially only the initial amorphous regions to create halo regions. The diffusion of dopant may be by laser annealing to locally melt only the amorphous region.
Preferably, the first amorphous regions and the dopant diffused therethrough extend beneath the sidewall insulators, and the second amorphous regions and the dopant diffused therethrough do not extend beneath the sidewall insulators. The halo region may be doped with a p-type dopant and the first and second amorphous regions may be doped with an n-type dopant to create an NFET, or the halo region may be doped with an n-type dopant and the first and second amorphous regions may be doped with a p-type dopant to create a PFET. Preferably, each of the halo regions and the source and drain regions have substantially uniform depths.
In a related aspect, the present invention provides a method for fabricating FETs with abrupt halos in which there is provided an initial FET structure having a substrate, a dielectric layer over a portion of the substrate, a gate over the dielectric layer, sidewall insulators on either side of and adjacent the dielectric layer and gate. The method includes creating initial amorphous regions in the substrate adjacent the sidewall insulators using ion implantation and implanting an n- or p-type dopant within the initial amorphous regions. The dopant is diffused throughout substantially only the initial amorphous regions by laser annealing to locally melt only the amorphous region to create halo regions extending to a desired depth in the substrate adjacent each of the sidewall insulators and beneath a portion of the dielectric layer. First amorphous regions are then created within a portion of each of the halo regions to a depth less than the halo regions. A dopant opposite the n- or p-type dopant used in the halo region is implanted in and diffused throughout only the first amorphous regions to create extension source and drain regions. Dielectric spacers are formed adjacent the sidewall insulators and second amorphous regions are created adjacent each of the dielectric spacers to a depth greater than the halo regions. A dopant opposite the n- or p-type dopant used in the halo region is implanted in and diffused throughout only the second amorphous regions to create source and drain regions.
The diffusion of dopant in the first and second amorphous regions may be by laser annealing to locally melt only the amorphous region. Preferably, the first amorphous regions and the dopant diffused therethrough extend beneath the sidewall insulators and the second amorphous regions and the dopant diffused therethrough do not extend beneath the sidewall insulators. The halo region may be doped with a p-type dopant and the first and second amorphous regions may be doped with an n-type dopant to create an NFET, or the halo region may be doped with an n-type dopant and the first and second amorphous regions may be doped with a p-type dopant to create a PFET. Preferably, each of the halo regions and the source and drain regions have substantially uniform depths.
The invention also includes a FET made by the aforementioned methods.
In another aspect, the present invention provides a FET comprising a substrate, a dielectric layer over a portion of the substrate, a gate over the dielectric layer and sidewall insulators on either side of and adjacent the dielectric layer and gate. Halo regions comprising an n- or p-type dopant extend to a desired depth in the substrate adjacent each of the sidewall insulators and beneath a portion of the dielectric layer. Extension source and drain regions are provided within a portion of each of the halo regions having a depth less than the halo regions. The extension source and drain regions are doped with a dopant opposite the n- or p-type dopant used in the halo region. Dielectric spacers are adjacent the sidewall insulators and source and drain regions are provided adjacent the dielectric spacers having a depth greater than the halo regions. The source and drain regions are doped with a dopant opposite the n- or p-type dopant used in the halo region. Preferably, the extension source and drain regions extend beneath the sidewall insulators and the deeper source and drain regions do not extend beneath the sidewall insulators. It is also preferred that the halo regions and the source and drain regions have substantially uniform depths.